I am currently trying to debug a hardfault on a cortex M7 running freertos. I have been using your great blog post and webinar on this subject and I have learnt a lot from it, so thank you very much for that. Although it has been really helpful and allowed me to improve my processes, I have not been to progress much in finding the cause of my hardfault.
Context:
I have a monitoring system that has async I2C coms, it was running stable until I changed the optimization from none to ‘optimize for debugging’ and now it triggers a hardfault. There are a couple things I can do to stop the hardfault occurring like, carrying out the i2c transactions sequentially or putting a delay between the read_start and read_end calls. Also if I simplify the logic for sensor selection the hardfault takes a lot longer to occur.
When I was using the debugger I found that putting breakpoints in certain places or stepping through the code in certain ways would cause the hardfault not to be triggered at the expected point and would push it back to occur later if the program was left to run freely.
When using the methods described in the blog post and webinar I found that the state of the fault registers and the back trace are not consistent each time I trigger the fault and the back trace contains functions that should not be present.
Questions:
Basically because of these inconsistencies and that I’m not very experienced with debugging programs at such a low level I am not sure how to proceed from here. I’m wondering is there anything that can be deduced from the behaviour I seen so far that may help me in progressing or are there any other methods I can try out?
Thanks for providing this platform and the great content.