Thank you for that very interesting article.
We have been adopting the NXP i.MX RT105x controllers for a long time now for many of our products.
The memory layout of these processors is much more complex than a classic controller (which usually has only flash+SRAM).
They only have built-in SRAM, the flash is external (we adopt 2MB QSPI chips).
SRAM in turn is divided into ITCM, DTCM and OnChipRAM. Although the dimensions can be configured, this is done statically with respect to FW.
For us, using the output of the size command can’t work. In fact both .text and .data and .bss are splitted between flash and the three RAM memories. For example .text is partly in flash and partly in ITCM (and hopefully no other memory). .data is in both DTCM and OCRAM.
What we’re interested in is knowing how full the memory regions are:
Memory region Used Size Region Size %age Used
BOARD_FLASH: 280964 B 2 MB 13.40%
SRAM_DTC: 122580 B 128 KB 93.52%
SRAM_ITC: 106112 B 128 KB 80.96%
SRAM_OC: 61444 B 256 KB 23.44%
but also know for each memory region how the allocated part is divided between .text, .data and .bss.
What strategy would you follow?
Our long-term goal would be to have a map of occupation of the memory regions that informs us how much the different compile units fill.
best regards
Max