# Cortex-M Exception Handling | Interrupt **URL:** \ **Category:** Blog\ **Created:** [September 4, 2019, 6:37am UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75 "2019-09-04T06:37:11Z")\ **Posts on this page:** 7\ **Page:** 1
**Author:** ![discobot](https://yyz2.discourse-cdn.com/flex030/user_avatar/community.memfault.com/discobot/32/1_2.png) [@discobot](https://community.memfault.com/u/discobot)\ **Post date:** [September 4, 2019, 6:37am UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/1 "2019-09-04T06:37:11Z")
Nearly all embedded systems at one point or another rely on the ability to handle asynchronous events. For example, it could be reading external sensor data from an accelerometer in order to count steps or handling periodic timer events to trigger a context switch for an RTOS. * * * This is a companion discussion topic for the original entry at [https://interrupt.memfault.com/blog/arm-cortex-m-exceptions-and-nvic](https://interrupt.memfault.com/blog/arm-cortex-m-exceptions-and-nvic) ---
**Author:** ![FelixBors](https://avatars.discourse-cdn.com/v4/letter/f/9de053/32.png) [@FelixBors](https://community.memfault.com/u/FelixBors)\ **Post date:** [December 2, 2019, 9:51pm UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/2 "2019-12-02T21:51:59Z")
Thank you Chris, very useful. ---
**Author:** ![radin](https://avatars.discourse-cdn.com/v4/letter/r/ed655f/32.png) [@radin](https://community.memfault.com/u/radin)\ **Post date:** [October 25, 2020, 12:52am UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/4 "2020-10-25T00:52:54Z")
Thanks a lot. Could you please explain more on how to configure a GPIO pin to trigger interrupts on NVIC? I mean how to find PIO’s corresponding bits in NVIC registers. ---
**Author:** ![tobermory](https://avatars.discourse-cdn.com/v4/letter/t/439d5e/32.png) [@tobermory](https://community.memfault.com/u/tobermory)\ **Post date:** [November 21, 2020, 6:36am UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/5 "2020-11-21T06:36:53Z")
Your post states that PendSV and Systick are triggered by software. While true for PendSV (and your code does it, normally this is done by ISRs serving I/O interrupts), I think that SysTick interrupts are hardware-sourced. Yes, you set up the Systick regs by software, but the event that fires the handler is a hardware one. In case anyone is unaware, all this material, and more, is detailed in Joseph Yiu’s amazing book on Cortex-M3/4 (definitive guide, 3rd ed). ---
**Author:** ![dnsglk](https://avatars.discourse-cdn.com/v4/letter/d/cdc98d/32.png) [@dnsglk](https://community.memfault.com/u/dnsglk)\ **Post date:** [February 17, 2021, 6:43pm UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/6 "2021-02-17T18:43:31Z")
Great article! Is my understanding correct, that the max depth the interrupts can be nested is the number of priority groups? I’m trying to wrap my head around on how to estimate the max stack size for interrupts considering the worst case scenario. Thanks, Denis ---
**Author:** ![JimYuill](https://avatars.discourse-cdn.com/v4/letter/j/74df32/32.png) [@JimYuill](https://community.memfault.com/u/JimYuill)\ **Post date:** [September 7, 2022, 5:00pm UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/7 "2022-09-07T17:00:50Z")
This is an excellent article, very clear and has needed info. It’s rare to find articles of this quality. Thanks! ---
**Author:** ![astasinos](https://avatars.discourse-cdn.com/v4/letter/a/ecccb3/32.png) [@astasinos](https://community.memfault.com/u/astasinos)\ **Post date:** [December 7, 2024, 7:08pm UTC](https://community.memfault.com/t/cortex-m-exception-handling-interrupt/75/8 "2024-12-07T19:08:55Z")
ARM recommends using both \_\_DSB and \_\_ISB memory barrier to guarantee a pended interrupt takes **immediate** effect. E.g. here PendSV. Is there a reason only \_\_ISB is used here?