FelixBors

Thank you Chris, very useful.

radin

Thanks a lot.
Could you please explain more on how to configure a GPIO pin to trigger interrupts on NVIC?
I mean how to find PIO’s corresponding bits in NVIC registers.

tobermory

Your post states that PendSV and Systick are triggered by software. While true for PendSV (and your code does it, normally this is done by ISRs serving I/O interrupts), I think that SysTick interrupts are hardware-sourced. Yes, you set up the Systick regs by software, but the event that fires the handler is a hardware one.

In case anyone is unaware, all this material, and more, is detailed in Joseph Yiu’s amazing book on Cortex-M3/4 (definitive guide, 3rd ed).

dnsglk

Great article!

Is my understanding correct, that the max depth the interrupts can be nested is the number of priority groups? I’m trying to wrap my head around on how to estimate the max stack size for interrupts considering the worst case scenario.

Thanks,
Denis

JimYuill

This is an excellent article, very clear and has needed info.
It’s rare to find articles of this quality.
Thanks!

astasinos

ARM recommends using both __DSB and __ISB memory barrier to guarantee a pended interrupt takes immediate effect. E.g. here PendSV.

Is there a reason only __ISB is used here?